In conventional IC package, either wire bonding or flip chip mounting are commonly used as the electrical connections between the chip and the substrate for different applications and functions of the IC chip.
As shown in FIG. 1, a conventional wire-bonding type IC package 100 includes a rigid PCB substrate 110, a chip 120, and a plurality of bonding wires 130 where the substrate 110 has a top surface 111 and a bottom surface 112. A slot 114 penetrates through the substrate 110 from the top surface 111 to the bottom surface 112. As shown in FIG. 2, a plurality of connecting pads 113 are disposed along the both sides of the slot 114 on the bottom surface 112 of the substrate 110. The chip 120 has a plurality of bonding pads 122 formed on the active surface 121. When the active surface 121 of the chip 120 is attached to the top surface 111 of the substrate 110, the plurality of bonding pads 122 are exposed from the slot 114. A plurality of bonding wires 130 are formed by wire-bonding through the slot 114 to electrically connect the bonding pads 122 of the chip 120 with the connecting pads 113 of the substrate 110. The chip 120 and the bonding wires 130 then are encapsulated by an encapsulant 140. The substrate 110 further includes a plurality of ball pads 115 formed on the bottom surface 112 for placing a plurality of solder balls 150 for SMT. However, the wire-bonding type IC package 100 can not meet the high speed requirements of high frequency electronic devices due to poor RLC characteristics of longer bonding wires 130.
As shown in FIG. 3, another conventional IC package 200 utilizing flip-chip mounting technology, includes a BT substrate 210, a bumped chip 220, and an underfill material 230 where the substrate 210 has multiple trace layers and PTHs (plated through hols) for double side electrical connections. As shown in FIG. 4, the substrate 210 has a plurality of PTHs 214 for electrical connections between the connection pads 213 on the top surface 211 and the ball pads 216 on the bottom surface 212 where a flip-chip area 215 is defined on the top surface 211 corresponding to the dimension of the bumped chip 220. The bumped chip 220 has an active surface 211 and a plurality of bumps 223 thereon where the bumps 223 are disposed on a plurality of redistributed UBM pads 222 in an array on the active surface 221. The redistributed UBM pads 222 are connected to original bonding pads of the chip 220 by redistribution trace layer (RDL), not shown in the figures. The bumped chip 220 is electrically connected to the substrate 210 by connecting the bumps 223 of the bumped chip 220 to the connecting pads 213 of the substrate 210. Then the underfill material 230 is formed in the gap between the chip 220 and the substrate 210 to encapsulate the bumps 223. A plurality of solder balls 240 are placed on a plurality of ball pads 216 on the bottom surface 212 of the substrate 210 for electrical connection to a printed circuit board. Even though the IC package 200 can meet the requirements of high frequency electronic devices, however, the multi-layer trace and PTH structure of the BT substrate 210 and RDL design of the bumped chip 220 are required where extra costs are added to manufacture of the IC package 200. Therefore, IC package 200 is not suitable for high frequency memory devices.